Multiplier Design using Machine Learning Alogorithms for Energy Efficiency

Simple item page
dc.contributor.authorJuma, Jane
dc.contributor.authorMdodo, R.M.
dc.contributor.authorGichoya, David
dc.date.accessioned2023-05-25T11:44:22Z
dc.date.available2023-05-25T11:44:22Z
dc.date.issued2023
dc.descriptionArticleen_US
dc.description.abstractDesigners primary goal is to develop the Adder cell with improved performance viz. speed, fixed rise and fall time, as it the fundamental block in VLSI design process. The dynamic logic circuits are far better than the static logic circuits because it consumes less power and speed performance also increased. But, cascading of several blocks in dynamic logic is found to be a wrong analysis. This drawback of increased complexity with mismatched cascading is overcome by using domino logic circuits. By using domino logic circuits, the reduction of noise margins and increase the speed performance of the circuit is achieved. In this paper, domino logic based Manchester carry chain adder (MCC) is designed using FinFET 18nm technology in Cadence virtuoso. It is noticed that 4-bit and an 8-bit Manchester Carry Chain Adder (MCC) using domino logic design consumes less power and reduction in the delay of the proposed circuit compared with the previous architecture. Implementation results reveal that the 4-Bit MCC Adder has delay of 79.45% less compared to the existed standard design and power consumption also reduced to 94.15%.en_US
dc.identifier.citationJuma J, Mdodo RM, Gichoya D. Multiplier Design using Machine Learning Alogorithms for Energy Efficiency. Journal of Complementary Research, Vol. 5, No. 1, 2023 (pp. 28-34)en_US
dc.identifier.otherDOI:https://doi.org/10.31838/jvcs/05.01.04
dc.identifier.urihttp://ir-library.ku.ac.ke/handle/123456789/25426
dc.language.isoenen_US
dc.publisherVLSIen_US
dc.subjectCadence virtuosoen_US
dc.subjectFinFETen_US
dc.subjectDynamic Logicen_US
dc.subjectDomino logicen_US
dc.subjectManchester Carry Chainen_US
dc.titleMultiplier Design using Machine Learning Alogorithms for Energy Efficiencyen_US
dc.typeArticleen_US
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
Multiplier Design using Machine Learning Alogorithms for Energy Efficiency.pdf
Size:
932.58 KB
Format:
Adobe Portable Document Format
Description:
Full text Article
Download
License bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
1.71 KB
Format:
Item-specific license agreed upon to submission
Description:
Download
Collections
RP-Department of Computing & Information Technology